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PIC16F870/871
DS30569B-page 84
2003 Microchip Technology Inc.
10.4
A/D Conversions
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D result register
pair will NOT be updated with the partially completed
A/D conversion sample. That is, the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers). After the A/D conversion
is aborted, a 2 TAD wait is required before the next
acquisition is started. After this 2 TAD wait, acquisition
on the selected channel is automatically started. The
GO/DONE bit can then be set to start the conversion.
In Figure 10-3, after the GO bit is set, the first time
segment has a minimum of TCY and a maximum of TAD.
FIGURE 10-3:
A/D CONVERSION TAD CYCLES
10.4.1
A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion of
the A/D conversion. This register pair is 16-bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D For-
mat Select bit (ADFM) controls this justification.
Figure 10-4 shows the operation of the A/D result justifi-
cation. The extra bits are loaded with ‘0’. When an A/D
result will not overwrite these locations (A/D disable),
these registers may be used as two general purpose
8-bit registers.
FIGURE 10-4:
A/D RESULT JUSTIFICATION
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
TAD1
TAD2
TAD3
TAD4
TAD5
TAD6
TAD7
TAD8
TAD9
Set GO bit
Holding capacitor is disconnected from analog input (typically 100 ns)
b9
b8
b7
b6
b5
b4
b3
b2
TAD10 TAD11
b1
b0
TCY to TAD
Conversion starts
ADRES is loaded
GO bit is cleared
ADIF bit is set
Holding capacitor is connected to analog input
10-bit Result
ADRESH
ADRESL
0000 00
ADFM = 0
0
2 1 0 7
7
10-bit Result
ADRESH
ADRESL
10-bit Result
0000 00
7
0 7 6 5
0
ADFM = 1
Right Justified
Left Justified
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